This invention relates generally to comparator circuits, and more particularly the invention relates to a comparator circuit which draws constant supply current and thus reduces sensitivity to non-zero power supply impedances.
Conventional switched capacitor comparator circuits such as that used in the LTC 1040, LTC 1090, and LTC 1290 manufactured by Linear Technology Corporation (Assignee herein) use a single CMOS inverter as the basic gain element. The well known "totem pole" characteristic of the inverter supply current causes the comparator to draw high current when the CMOS inverter is near its null point and low current when the CMOS inverter is away from its null point. The poor power supply rejection ratio (PSRR) of the inverter makes the comparator very sensitive to power supply variations created by the variation in supply current drawn by the comparator or a neighboring comparator on the same chip. This sensitivity to self-created power supply perturbations creates the need for expensive, large value, high quality decoupling capacitors and can result in more difficult supply decoupling and wiring in the use of the chip.
Heretofore, solutions to the problem focused on reducing the sensitivity of the comparator to supply variations, for example by using differential amplification. However, these approaches adversely affect simplicity of the circuit, easy single supply implementation, ease of auto zeroing, and compatibility with existing system architectures.